A Dynamic Memory Allocation Optimization Mechanism Based on Spark

Spark is a distributed data processing framework based on memory. Memory allocation is a focus question of Spark research. A good memory allocation scheme can effectively improve the efficiency of task execution and memory resource utilization of the Spark. Aiming at the memory allocation problem in the Spark2.x version, this paper optimizes the memory allocation strategy by analyzing the Spark memory model, the existing cache replacement algorithms and the memory allocation methods, which is on the basis of minimizing the storage area and allocating the execution area according to the demand. It mainly including two parts: cache replacement optimization and memory allocation optimization. Firstly, in the storage area, the cache replacement algorithm is optimized according to the characteristics of RDD Partition, which is combined with PCA dimension. In this section, the four features of RDD Partition are selected. When the RDD cache is replaced, only two most important features are selected by PCA dimension reduction method each time, thereby ensuring the generalization of the cache replacement strategy. Secondly, the memory allocation strategy of the execution area is optimized according to the memory requirement of Task and the memory space of storage area. In this paper, a series of experiments in Spark on Yarn mode are carried out to verify the effectiveness of the optimization algorithm and improve the cluster performance.     

Mechanical Assembly of Thermo‐Responsive Polymer‐Based Untethered Shape‐Morphing Structures

Shape‐morphing robotic structures can provide innovative approaches for various applications ranging from soft robotics to flexible electronics. However, the programmed deformation of direct‐3D printed polymer‐based structures cannot be separated from their subsequent conventional shape‐programming process. This work aims to simplify the fabrication process and demonstrates a rapid and adaptable approach for building stimulus‐responsive polymer‐based shape‐morphing structures of any shape. This is accomplished through mechanically assembling a set of identical self‐bending units in different patterns to form morphing structures using auxiliary hard connectors. A self‐bending unit fabricated by a 3D printing method can be actuated upon heating without the need for tethered power sources and is able to transform from a flat shape to a bending shape. This enables the assembled morphing‐structure to achieve the programmed integral shape without the need for a shape‐programming process. Differently assembled morphing structures used as independent robotic mechanisms are sequentially demonstrated with applications in biomimetic morphing structures, grasping mechanisms, and responsive electrical devices. This proposed approach based on a mechanical assembling method paves the way for rapid and simple prototyping of stimulus‐responsive polymer‐based shape‐morphing structures with arbitrary architectures for a variety of applications in deployable structures, bionic mechanisms, robotics, and flexible electronics.     

Fabrication of poly(ε‐caprolactone) (PCL)/poly(propylene carbonate) (PPC)/ethylene‐α‐octene block copolymer (OBC) triple shape memory blends with cycling performance by constructing a co‐continuous phase morphology

In this paper, a triple shape memory material was prepared by ultra‐simple melt blending from poly(ε‐caprolactone) (PCL), poly(propylene carbonate) (PPC) and ethylene‐α‐octene block copolymer (OBC). The obtained material possessed a co‐continuous phase morphology and presented an excellent triple shape memory effect (triple‐SME). Theoretical prediction demonstrated that a special continuous phase morphology could be constructed by adjusting the proportions of the blend. Moreover, the results indicated that a close relationship existed between the phase morphology and the triple‐SME of PCL/PPC/OBC. The sample with 35 vol% PPC content contributed to the formation of a continuous phase morphology and exhibited the optimal triple‐SME. Additionally, the sample PCL/PPC/OBC (32.5/35/32.5) showed outstanding structure and performance stability during cycle loading–unloading tests, which evidenced the prominent cycling shape memory property (nearly 100% shape fixing and recovery of temporary shape). Overall, this work could provide an efficient, convenient and recyclable method to obtain high‐performance shape memory materials. © 2020 Society of Chemical Industry     

A novel low-latency DRAM based on the bitline-discharge rate

As well known by computer architects, the performance gap between the processor and the memory has been increasing over the years. This causes what is known as the memory wall. In order to alleviate the problem, a novel fast readout scheme is proposed in this article for the single-transistor single-capacitor dynamic random-access memory (1T-1C DRAM) cells. The proposed scheme works in the current domain in which the difference between the discharging rates of the bitline in the cases of ‘1’ and ‘0’ readings is detected. The proposed scheme is analysed quantitatively and compared with the conventional readout scheme. It is verified by simulation adopting the 45 nm CMOS Berkley predictive-technology model (BPTM) and shows 44 and 7.7% reductions in the average read-access and cycle times, respectively, as compared to the conventional readout scheme. It is also shown that the power is saved according to the proposed scheme if the probability of occurrence of ‘0’ storage exceeds 66.7%. This minimum value can be alleviated, however, at the expense of a smaller saving in the average read-access time. The impacts of process variations and technology scaling are also taken into account.     

苯并噁嗪树脂的合成及在形状记忆聚合物中的应用研究进展

苯并噁嗪树脂作为一类新型的热固性树脂，具有分子设计性强、阻燃性能和耐腐蚀性能优异、固化时不需要强酸、无小分子放出等优点，在航空、建筑、电子等领域获得了广泛应用。本文主要介绍了苯并噁嗪单体的合成方法（溶剂法、无溶剂法和悬浮法）、降低苯并噁嗪开环聚合温度的方法（合成具有特殊基团的苯并噁嗪单体、添加催化剂）及苯并噁嗪树脂在形状记忆聚合物中的应用（与其他聚合物混合，纯苯并噁嗪化学改性），对苯并噁嗪形状记忆聚合物目前存在的问题进行了概述并对苯并噁嗪形状记忆聚合物的发展前景做出了展望。     

Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology

1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm² is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm² array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall V_min of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances.     

基于强化学习的电力市场信息披露程度对市场成员交易行为影响研究

基于信息披露的主体框架，分析披露体系中具体的供需信息对于市场成员的引导作用。建立日前市场的双层竞价优化模型，采用强化学习的方法，通过市场中有无关键供求信息披露对于发电商报价预期的影响，推演模拟不同信息披露程度下发电商报价行为，然后从策略演化过程、策略偏离度以及策略收敛速度3个角度进行信息披露程度对市场成员交易行为影响的定量分析，验证市场供需信息的发布程度对于市场成员的引导作用，最后基于推演结果进行总结，并对我国信息披露的建设提出建议与思考。     

Resistive switching characteristics of ZnO–graphene quantum dots and their use as an active component of an organic memory cell with one diode-one resistor architecture

We investigated the resistive switching characteristics of a polystyrene:ZnO–graphene quantum dots system and its potential application in a one diode-one resistor architecture of an organic memory cell. The log–log I–V plot and the temperature-variable I–V measurements revealed that the switching mechanism in a low-current state is closely related to thermally activated transport. The turn-on process was induced by a space-charge-limited current mechanism resulted from the ZnO–graphene quantum dots acting as charge trap sites, and charge transfer through filamentary path. The memory device with a diode presented a ∼10³ I_ON/I_OFF ratio, stable endurance cycles (10² cycles) and retention times (10⁴ s), and uniform cell-to-cell switching. The one diode-one resistor architecture can effectively reduce cross-talk issue and realize a cross bar array as large as ∼3 kbit in the readout margin estimation. Furthermore, a specific word was encoded using the standard ASCII character code.     

Fix-and-relax approaches for controlled tabular adjustment

Controlled tabular adjustment (CTA) is a relatively new protection technique for tabular data protection. CTA formulates a mixed integer linear programming problem, which is challenging for tables of moderate size. Even finding a feasible initial solution may be a challenging task for large instances. On the other hand, end users of tabular data protection techniques give priority to fast executions and are thus satisfied in practice with suboptimal solutions. This work has two goals. First, the fix-and-relax (FR) strategy is applied to obtain good feasible initial solutions to large CTA instances. FR is based on partitioning the set of binary variables into clusters to selectively explore a smaller branch-and-cut tree. Secondly, the FR solution is used as a warm start for a block coordinate descent (BCD) heuristic (approach named FR+BCD); BCD was confirmed to be a good option for large CTA instances in an earlier paper by the second and third co-authors (Comput Oper Res 2011;38:1826–35 [23]). We report extensive computational results on a set of real-world and synthetic CTA instances. FR is shown to be competitive compared to CPLEX branch-and-cut in terms of quickly finding either a feasible solution or a good upper bound. FR+BCD improved the quality of FR solutions for approximately 25% and 50% of the synthetic and real-world instances, respectively. FR or FR+BCD provided similar or better solutions in less CPU time than CPLEX for 73% of the difficult real-world instances.     

Non-proportional multiaxial whole-life transformation ratchetting and fatigue failure of super-elastic NiTi shape memory alloy micro-tubes

Experimental observations are performed to investigate the non-proportional multiaxial whole-life transformation ratchetting and fatigue failure of superelastic NiTi SMA micro-tubes in stress-controlled loadings at human-body temperature (310 K). The effects of axial mean stress and stress hold on the whole-life transformation ratchetting and fatigue life are investigated with uniaxial, torsional and five different multiaxial loading paths. The results show that the stress holds on the upper or lower transformation plateaus will both promote forward and reverse transformation, and lead to shorter fatigue life. The multiaxial fatigue lives of NiTi shape memory alloy depend significantly on loading paths and applied stress levels.